1. Field of the Invention
The present invention relates to computers, and more particularly, pertains to resistive termination of CPU data buses and CPU address buses.
2. Description of the Prior Art
In prior art computer operations, the data buses have had a nominal termination between the power supply, Vsupply and the data bus. Regardless of the operations, this nominal termination was constant and fixed, resulting in slower running computers because of a fixed and constant nominal termination and hotter running computers because of power consumption.
The present invention overcomes the disadvantages of the prior art by providing an adaptive bus termination where a reduced termination resistor is switched in and out during predetermined periods of operation, such as, for example read operations for a CPU data bus and hold acknowledge cycles for a CPU address bus.